Saturday, August 06, 2011

Did you ever think? How Intel's chips are made

This is an illustration of how chips are made. Articles and pictures below demonstrate the stages of the process of how to produce a CPU (central processing unit), which is used in every PC in the world today. You'll catch a glimpse of some incredible work that is done every day at its plant at Intel.

1. Sand
Sand - especially Quartz - has high percentages of Silicon in the form of Silicon dioxide (SiO2) and this is base material for semiconductor production.

Sand - about 25% of the Silicon that is a compound the second largest - after oxygen - in the face of the earth

2. Silikon Cair

Silicon is purified in multiple steps to finally nencapai quality which is called Electronic Grade Silicon (EGS). EGS may only contain a foreign atom per one billion Silicon atoms. In the picture below you can see how a large crystal grown from molten silicon is purified. The result is a single crystal is called Ingot.

Silikon cair - skala: level wafer (~300mm / 12 inch)

3. Single Crystal line Silicon-Ingot

An ingotis made of Electronic Grade Silicon. An ingot weighs about 100kilograms(220pounds) and has apurity of 99.9999 % Silicon.

Mono-crystal Silicon Ingot -- scale: wafer level (~300mm / 12 inch)

4. Ingot incision

Ingots and then sliced ​​into individual silicon discs called wafers..

Ingot Slicing -- scale: wafer level (~300mm / 12 inch)

5. Wafer

Wafer-wafer are polished to flaw lesss mooth surfaces of glass mirror.Intel to buy wafer-wafer manufacturing ready from third party companies. High-k/metal 45nm Gate Process complicated by Intel uses wafers with a diameter of200 millimeters. When Intel began making chips the company printed circuitson a wafer 50 millimeters. Andfor now using 300mm wafers resulting incost savings per-chip.

Wafer -- scale: wafer level (~300mm / 12 inch)

6. Apply Photo Resist

Fluid (blue) that poured onto the wafer while it is playing is a process of photo resist as we know it from film photography. Wafer played during this phase to make it very thin and even a photo resist layer.

Applying Photo Resist -- scale: wafer level (~300mm / 12 inch)

7. Exposure

The results of the photo resist is exposed to ultraviolet light (UV. chemical reaction triggered by the stage in the process, similar to what happens in the film material on a camera when you press the shutter button. Results of photo resist is exposed to UV rays will be able to dissolve . Exposure solved using a stencil mask that serves as the stage of this process. When used with UV light, the mask forming circuit patterns on each layer varies from the microprocessor. A lens (middle) reduces the image of the mask. So that is printed on above the wafer typically is four times smaller than the linear patterns of the mask.

Exposure -- scale: wafer level (~300mm / 12 inch)

8. Exposure

Although usually hundreds of microprocessors can be produced from a single wafer, this picture story will focus on only a small part of a microprocessor, which is on a transistor or a part thereof. A transistor acts as a switch, controlling the flow of electric current in a computer chip. Researchers at Intel have developed transistors so small that about 30 million transistors can fit on the head of a pin.

Exposure -- scale: transistor level (~50-200nm)

9. Cleaning Photo Resist

Photo resist sticking perfectly dissolved by a solvent.This process leaves a pattern of photo resist is made mask.

Washing off of Photo Resist -- scale: transistor level (~50-200nm)

10. Etching

Photo resist to protect material that should not be scratched. Materials left behind will be scratched (disketch) with chemicals.

Etching -- scale: transistor level (~50-200nm)

11. Delete Photo Resist

AfterEtchingprocessphoto resistis removedandthe desired shape becomesvisible.

Removing Photo Resist -- scale: transistor level (~50-200nm)

12. Apply Photo Resist

There is a photo resist (blue) was applied here, the exposed photo resist is exposed and cleaned before the next stage. Will protect the photo resist material that should not be implanted ions.

Applying Photo Resist -- scale: transistor level (~50-200nm)

13. planting Ion

Through a process called "ion implantation" (a form of a process called doping), areas of silicon wafer are bombarded with the "dirt" various chemical called ions. The ions are implanted in the silicon wafer to change the silicon in these areas conducts electricity. Ions are shot in the upper surface of the wafer at high speed. An electric field accelerates the ions to a speed of 300,000 km / h.

Ion Implantation -- scale: transistor level (~50-200nm)

14. Eliminating Photo Resist

After planting ion, photo resist is removed and the material should be doped (green) has a foreign atoms that have been embedded (note the fleeting color variations).

Removing Photo Resist -- scale: transistor level (~50-200nm)

15. The transistor is Ready

This transistor is close to the end. Three holes have been formed (the etching) in the insulation layer (magenta) on top of the transistor. Three holes will be filled with copper that will connect it to other transistors.

Ready Transistor -- scale: transistor level (~50-200nm)

16. Electroplating

Wafer-wafer is put into a copper sulfate solution at this point. Copper ions implanted above the transistor through a process called electroplating. Copper ions move from the positive terminal (anode) to the negative terminal (cathode) are presented by the wafer.

Electroplating -- scale: transistor level (~50-200nm)

17. Stage After Electroplating

On the surface of the wafer, copper ions to form into a thin layer of copper.

After Electroplating -- scale: transistor level (~50-200nm)

18. Polishing

Material in excess of the previous process eliminated.

Polishing -- scale: transistor level (~50-200nm)

19. Metal coating

Layers of metal formed to interconnect (like wires) between the transistors. How the connections it is connected is determined by the team that developed the design and architecture funsionalitas particular processor (eg Intel ® Core ™ i7 Processor). While computer chips look very flat, in fact in it has more than 20 layers that make up the complex circuits. If you look at the enlargement of a chip, you'll find an intricate network of circuit lines and transistors are similar layered highway system in the future.

Metal Layers -- scale: transistor level (six transistors combined ~500nm)

20. Wafer Testing

Part of a wafer that had already been taken to do test this functionality. In this test phase, the patterns in put into each chip and the response of the chip is monitored and compared with a predefined list.

Wafer Sort Test -- scale: die level (~10mm / ~0.5 inch)

21. Wafer slicing

Wafer sliced ​​into sections called Die.

Wafer Slicing -- scale: wafer level (~300mm / 12 inch)

22. Separating Die Failed Fungsion

Die-die during a test pattern that responds properly to be taken to the next stage.

Discarding faulty Dies -- scale: wafer level (~300mm / 12 inch)

23. Individual Die

This is a single die that has been so in the previous stage (chopping). Die visible here is the die of an Intel ® Core™ i7.

Individual Die -- scale: die level (~10mm / ~0.5 inch)

24. Packaging

The base, die and heatspreader combined into a complete processor. The bottom of the green form electrical and mechanical interfaces for the processor to interact with computer systems (PCs). Silver heatspreader serves as a cooling (cooler) to maintain optimum temperature for the processor.

Packaging -- scale: package level (~20mm / ~1 inch)

25. Prosessor

This is a ready-made processor (Intel ® Core ™ i7 Processor). A microprocessor is the most complex product ever created on earth. In fact, it takes hundreds of steps - only the most important parts are shown in this article - which is done in a work environment the cleanest in the world, a microprocessor lab.

Processor -- scale: package level (~20mm / ~1 inch)

26. Class Testing

During this last test, the processors will be tested for their key characteristics (including test power consumption and maximum frequency).

Class Testing -- scale: package level (~20mm / ~1 inch)

27. Binning

Based on the test results of class testing, the processor with the same capabilities in transporting Trays collected on the same.

Binning -- scale: package level (~20mm / ~1 inch)

28. Retail Package

Processors have been prepared and passed the test had ended up in the marketing channels in one box packaging.

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